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132
ATmega8515(L)
2512K–AVR–01/10
be cleared, and SPIF in SPSR will become set. The user will then have to set MSTR to
re-enable SPI Master mode.
Bit 3 – CPOL: Clock Polarity
When this bit is written to one, SCK is high when idle. When CPOL is written to zero,
SCK is low when idle. Refer to Figure 62 and Figure 63 for an example. The CPOL func-
tionality is summarized below:
Bit 2 – CPHA: Clock Phase
The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading
(first) or trailing (last) edge of SCK. Refer to Figure 62 and Figure 63 for an example.
The CPHA functionality is summarized below:
Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0
These two bits control the SCK rate of the device configured as a Master. SPR1 and
SPR0 have no effect on the Slave. The relationship between SCK and the Oscillator
Clock frequency f
osc is shown in the following table:
Table 56. CPOL Functionality
CPOL
Leading Edge
Trailing Edge
0
Rising
Falling
1
Falling
Rising
Table 57. CPHA Functionality
CPHA
Leading Edge
Trailing Edge
0
Sample
Setup
1
Setup
Sample
Table 58. Relationship Between SCK and the Oscillator Frequency
SPI2X
SPR1
SPR0
SCK Frequency
00
0
f
osc/4
00
1
f
osc/16
01
0
f
osc/64
01
1
f
osc/128
10
0
f
osc/2
10
1
f
osc/8
11
0
f
osc/32
11
1
f
osc/64
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